In a memory, such as a random access memory (RAM), or a semiconductor integrated circuit equipped with a RAM, a spare memory area (redundancy area), is provided from the outset, for the columns and/or rows in a memory cell array, and failed cells of the memory cell array, detected by a wafer test, for example, are replaced by redundancy cells, thereby repairing failed bits and improving device yield. In order to enable a plural number each of row addresses and column addresses to be repaired, a plural number of redundancy addresses are provided for rows and for columns, respectively.
A plural number of redundancy ROM (Read Only Memory) circuits are provided corresponding to a plural number of redundant addresses, respectively. In one redundancy ROM circuit, there is recorded the information of one address, which is a row address or a column address, also termed a repair address, which is to be replaced by a redundant address. In programming the redundancy ROM circuit, those fuses corresponding to bit positions of address bits of the address information in the redundancy ROM circuit, out of a plural number of fuses corresponding to the number of bits of the address information in the redundancy ROM circuit, are blown by a laser beam. For example, the fuse corresponding to the bit with an address value of 1 is blown, while the fuse corresponding to the bit with an address value of 0 is unblown. The value of the fuse circuit blown is read out e.g. to a HIGH level, while that of the fuse circuit unblown is read out e.g. to a LOW level.
If, during the use of the memory, a redundancy enable signal is activated by, for example, an external command, the access address supplied from outside, is checked as to whether or not it is coincident with the address information programmed in the redundancy ROM circuit. In case of coincidence, a hit signal (redundancy selection signal) is activated, and the redundant address, associated with the activated redundancy selection signal, is selected. If the redundancy address is selected, address decoding by a row or column decoder is halted and the redundancy address of the row or the column associated with the redundancy selection signal is selected. If the redundancy enable signal has been activated and the accessed address is not coincident with any address information programmed in the plural number of the redundancy ROM circuits, the normal access to the normal memory array is performed.
Meanwhile, the general configuration of the redundancy ROM circuit, and the RAM, including the redundancy ROM circuit, is well-known to those skilled in the art. Reference may be made to the description of Patent Publication 1 of the present Assignee as for the overall configuration of a semiconductor memory having a redundancy circuit, a redundancy decoder, a redundancy ROM circuit (fuse ROM) or a decoder killer circuit. Hence, in the present specification, the description of the redundancy ROM circuit based on drawings is dispensed with.
Up to now, it has been practiced to check if the input address is to be replaced by the redundant address, using a roll call test and the like. Patent Publication 2 discloses a constitution as a semiconductor memory device for checking if the fuses of a redundancy circuit have been set to correct states, in which the program information of the fuses provided in the redundancy circuit is checked in the second roll call test mode and the results of the check are output to an output terminal.
[Patent Publication 1] JP Patent Kokai Publication No. JP-P2004-296051A
[Patent Publication 2] JP Patent Kokai Publication No. JP-P2006-107664A